Many SRAM circuits employ bitline pull-up circuitry to raise SRAM bitlines selectively to desired voltage levels. A conventional circuit of this type is shown in FIG. 1. In the FIG. 1 circuit, the drains of NMOS transistors N1, N2, N3, and N4 are connected to a line maintained at voltage V.sub.cc. The sources of transistors N1, N2, N3, and N4 are connected, respectively, to bitlines B.sub.1, -B.sub.1, B.sub.2, and -B.sub.2. Voltage V.sub.a1 (applied to the gate of transistor N1) is controlled in order to switch transistor N1 on and off selectively, thereby pulling bitline B.sub.1 selectively up to a voltage level substantially equal to V.sub.cc -V.sub.Th (where V.sub.Th is the threshold voltage between the gate and source of transistor N1, at which N1 begins to conduct). Similarly, voltages V.sub.a2, V.sub.a3, and V.sub.a4 (applied to the gates of transistors N2, N3, and N4, respectively) are controlled to switch transistors N2, N3, and N4 on and off, thereby pulling bitlines -B.sub.1, B.sub.2, and -B.sub.2 selectively up to V.sub.cc -V.sub.Th.
FIG. 2 is a conventional variation on the circuit of FIG. 1, which employs resistors to reduce the current I.sub.cc during normal circuit operation. Specifically, the FIG. 2 circuit employs resistor R1 (connected between voltage V.sub.cc and the drain of transistor N1), resistor R.sub.2 (connected between bitline B.sub.1 and the source of transistor N1), resistor R3 (connected between voltage V.sub.cc and the drain of transistor N2), and resistor R4 (connected between bitline -B.sub.1 and the source of transistor N2) to reduce the current I.sub.cc. In variations on FIG. 2 circuit, one or more of the resistors R1, R2, R3, and R4 can be omitted.
SRAM cells can be disturbed by electron or hole carriers generated by nearby junction leakage or other carrier generation mechanisms. The effect of such disturbances on an SRAM cell is less severe to the extent that the bitlines are pulled up to lower voltages. By reducing bitline voltages during normal operation, hot electron degradation on circuitry connected to the bitlines (e.e., SRAM cell pass gates) is also reduced, and good voltage matches to the input of sense amplifiers (not shown) can be achieved.
Another type of conventional bitline pull-up circuit is shown in FIG. 3. In FIG. 3, a line maintained at voltage V.sub.cc is connected to the drain of NMOS transistor N1, and the source of transistor N1 is connected to the common source of PMOS transistors P1, P2, P3, and P4 (which is at the voltage level V.sub.com). The drains of transistors P1, P2, P3, and P4 are connected, respectively, to bitlines B.sub.1, -B.sub.1, B.sub.2, and -B.sub.2. The voltages V.sub.e1, V.sub.e2, V.sub.e3, and V.sub.e4 supplied to the PMOS transistor gates are controlled to switch transistors P1, P2, P3, and P4 on and off, respectively, thereby pulling bitlines B.sub.1, -B.sub.1, B.sub.2, and -B.sub.2 selectively up to a voltage substantially equal to V.sub.com.
FIG. 4 is a conventional variation on the FIG. 3 circuit, in which resistors are employed to reduce the currents I.sub.cc and I.sub.com during operation thereof. Specifically, the FIG. 4 circuit employs resistor R1 (connected between voltage V.sub.cc and the drain of transistor N1), resistor R2 (connected between the source of transistor N1 and the common source of transistors P1 and P2), resistor R3 (connected between voltage V.sub.com and the source of transistor P1), resistor R4 (connected between bitline B and the drain of transistor P1), resistor R5 (connected between voltage V.sub.com and the source of transistor P2), and resistor R6 (connected between bitline -B and the drain of transistor PN2) to reduce said currents. In variations on FIG. 4 circuit, one or more of the resistors R1, R2, R3, R4, R5, and R6 can be omitted. The FIG. 4 circuit has the advantages of reduced disturbance (due to nearby junction leakage) and reduced hot electron degradation discussed above with reference to FIG. 2.
In variations on the circuits of FIGS. 1 through 4, one or more of the NMOS pull-up transistors are replaced by bipolar transistors. In each such circuit, a line maintained at voltage V.sub.cc is preferably connected to the collector of the bipolar transistor, the emitter of each bipolar transistor is preferably connected (optionally in series with a resistor) to one of the bitlines (or to the common source of two or more PMOS transistors which are in turn connected to the bitlines), and the base of each bipolar transistor is preferably connected to one of the control voltages V.sub.a or V.sub.e. However, such bipolar transistor circuits are subject to the same disadvantages and limitations as are the NMOS transistor circuits of FIGS. 1 through 4.
In order to conduct various tests of circuitry (for example, SRAM circuitry) to which bitlines are connected, it would be desirable to pull the bitlines up to a higher level than its normal operating voltage level. For example, it may be desired to screen out weak parts (e.g., parts having excessively high load resistance or excessively high junction leakage). It may also be useful to accelerate hot electron and other degradations of SRAM cells during burn-in or lifetime testing by increasing the bitline voltage level. However, the above-discussed conventional circuits have the disadvantage of being incapable of operating in both a test mode in which they raise bitlines to higher voltage levels without significant external V.sub.cc increase, and a normal operating mode in which they raise bitlines selectively to relatively low voltage levels.